(1) Field of the Invention
The present invention relates to a processing apparatus for use in an LSI such as a microprocessor.
(2) Description of the Related Art
In recent times, the performance of processing apparatuses such as microprocessors and digital signal processors (DSP) has been improving from year to year. With high-performance microprocessors in particular, the improvement of processing capability is realized through the addition of augmentative circuit elements and functions such as a large-capacity cache memory, a superscalar architecture, and a speculative instruction execution mechanism. On the other hand, the increase in power consumption due to the addition of such augmentative circuit elements has become a problem for the LSI and systems equipped with an LSI. Accordingly, the suppression of power consumption while realizing required performance has become an issue in the development of microprocessors.
With respect to this issue, technology such as that disclosed in Japanese Laid-Open Patent Application No. 8-77000 Publication (page 2 to 4 and FIG. 4) is being used in the conventional microprocessor. More specifically, the conventional processor includes an instruction cache which is placed inside the processor and which provides instructions at extremely high speed, a branch target buffer which holds data such as a predicted branch target instruction and a history bit, and a prefetch buffer which holds the instructions provided by the instruction cache for decoding using an instruction decoder. Such microprocessors have a method for reducing the power consumed by the processor by reducing unnecessary prefetch access of the instruction cache when a branch instruction is executed. To be more specific, with respect to each branch instruction to be executed, in the case where the instruction for the predicted branch target address is present in the prefetch buffer, accesses to the instruction cache are eliminated and power consumption is reduced by performing a control which locks the prefetch buffer and a control that prohibits prefetching, and providing the instruction for the branch target address from the prefetch buffer instead of the instruction cache.
In the conventional processor circuit which is configured in the manner described above, reduction of power consumed by the processor is realized by prohibiting unnecessary prefetching to the instruction cache. However, in a situation where the processor is actually being used, the upper limit of the processing details required from such processor, in other words, the processing performance of the processor, and the allowable amount of power consumption during operation of the processor, are fixed. In such a usage situation, the required processing performance can be sufficiently brought out through the conventional method of prohibiting unnecessary prefetching. However, with regard to power consumption, there are cases where a sufficient reduction effect is not obtained and it is not possible to go below the allowable amount of power consumption.
In addition, although a method which extends the cycle time of a CPU clock provided to a processor (CPU) exists as a method for reducing power consumption, there are cases where, depending on the details of a program executed by the processor, and the condition under which it is executed, the required processing performance cannot be obtained.